1. Field of the Invention
The present invention relates to semiconductor devices, and, more particularly, to a structure of a semiconductor device provided with a thin film transistor (hereinafter referred to as TFT) and a method of manufacturing the same.
2. Description of the Background Art
A memory cell in a SRAM (Static Random Access Memory) will be described in the following as an example of a semiconductor device provided with a thin film transistor. FIG. 32 is an equivalent circuit diagram of a general memory cell in a SRAM. Referring to FIG. 32, a memory cell in a SRAM has a pair of CMOS inverters. One of the CMOS inverters has a driver MOS transistor Q.sub.2 and a load thin film transistor Q.sub.1. The other CMOS inverter has a driver MOS transistor Q.sub.4 and a load thin film transistor Q.sub.3. The gates of transistors Q.sub.2, Q.sub.1 in one CMOS inverter are cross-connected to a common storage node N.sub.2 of transistors Q.sub.4, Q.sub.3 in the other CMOS inverter, and the gates of transistors Q.sub.4, Q.sub.3 in the other CMOS inverter are cross-connected to a common storage node N.sub.1 of transistors Q.sub.2, Q.sub.1 in the one CMOS inverter to implement a flip-flop circuit. The sources of load thin film transistors Q.sub.1, Q.sub.3 are connected to a power supply Vcc. Sources of driver MOS transistors are connected to a ground potential Vss. Transfer MOS transistors Q.sub.5, Q.sub.6 are connected, respectively, to storage nodes N.sub.1, N.sub.2 in the flip-flop circuit. The gates of transfer MOS transistors Q.sub.5, Q.sub.6 are connected to a word line 30. The drain regions of transfer MOS transistors Q.sub.5, Q.sub.6 are connected, respectively, to bit lines 31, 32.
FIG. 31 is a cross sectional view illustrating a specific structure of the memory cell illustrated in FIG. 32. The illustrated structure of the memory cell is similar to a structure of a memory cell disclosed in a Memory Cell with Polysilicon Thin Film Transistor (TFT) for a 4 Mbit Ram and so on, Denshi Joho Tsushin Gakkai Gijyutsu Kenkyu Hokoku, Shingaku Giho Vol. 90, No. 48, 1990, for example, and it is a typical cross section illustrated schematically. Referring to FIG. 31, a driver MOS transistor Q.sub.2 and a transfer MOS transistor Q.sub.6 formed on a main surface of a semiconductor substrate 1 and a load thin film transistor Q.sub.3 arranged in an upper layer with a first interlayer insulating layer 12 interposed therebetween are illustrated in the drawing. Driver MOS transistor Q.sub.2 formed on the main surface of silicon substrate 1 includes a gate electrode 6a, a pair of source/drain regions 9a, 9a, and a gate insulating layer 5a. Transfer MOS transistor Q.sub.6 formed on the main surface of silicon substrate 1 includes a gate electrode 6b, a pair of source/drain regions 9b, 9b, and a gate insulating layer 5b. The memory cell is characterized by the structure in which the load thin film transistor is formed above the substrate with first interlayer insulating layer 12 interposed therebetween. Thin film transistor Q.sub.3 includes a gate electrode 13 formed on the surface of first interlayer insulating layer 12, a gate insulating layer 14 formed on the surface of gate electrode 13, and a polycrystalline silicon layer 15 formed on the surface of gate insulating layer 14. In polycrystalline silicon layer 15, a channel region 15a is formed in a position opposite gate electrode 13, and a pair of source/drain regions 15b, 15b is formed on both sides of channel region 15a. Each of source/drain regions 15b, 15b in polycrystalline silicon layer 15 extends to a predetermined position to serve as an interconnection layer. Specifically, as illustrated, one impurity region 15b is connected through a contact electrode 11 to source/drain region 9b of transfer MOS transistor Q.sub.6.
A thick second interlayer insulating layer 16 is formed on the surface of thin film transistor Q.sub.3. An aluminum interconnection layer 20 is connected, through a contact hole formed in second interlayer insulating layer 16 and through a barrier metal layer 19, to source/drain region 9b of transfer MOS transistor Q.sub.6. The surface of aluminum interconnection layer 20 is covered with a passivation film 21.
However, in the memory cell as illustrated in FIG. 31, the surface of polycrystalline silicon layer 15 in thin film transistor Q.sub.3 is oxidized to form a silicon oxide film 22, and, as a result, there is a problem of a reduced thickness of polycrystalline silicon layer 15. A state of formation of silicon oxide film 22 will be described in the following.
FIGS. 33 and 34 are cross sectional views illustrating a main manufacturing process of the memory cell in a SRAM illustrated in FIG. 31. First, referring to FIG. 33, a polycrystalline silicon layer is formed on the surface of first interlayer insulating layer 12 by a CVD (Chemical Vapor Deposition) process. Then, the polycrystalline silicon layer is patterned to form a gate electrode 13. A gate insulating layer 14 is formed on the surface of gate electrode 13 by a CVD process. A polycrystalline silicon layer 15 is formed by a CVD process. Then, polycrystalline silicon layer 15 is patterned using a photolithography process and an etching process. Then, a predetermined region is covered with a resist mask 24, and then, p-type impurity ions 25 are introduced into polycrystalline silicon layer 15. Source/drain regions 15b, 15b of thin film transistor Q.sub.3 are formed by doing this.
Then, as illustrated in FIG. 34, the resist mask is removed, and then, a BPSG (Boro-Phospho Silicate Glass) layer 16 is formed on the whole surface by a CVD process. Large steps are formed on the surface of BPSG layer 16 in accordance with the stepped shape of the surface of the lower layer. Accordingly, heat treatment is carried out for flattening the surface of BPSG layer 16. The heat treatment for flattening is carried out in an atmosphere of water vapor at a temperature in the range of 850.degree. C. to 900.degree. C. for about 20 to 30 minutes, for example. The heat treatment causes the surface of softened BPSG to reflow to be flattened.
However, in such a flattening process, oxygen in the atmosphere is diffused into the BPSG layer and reaches the surface of polycrystalline silicon layer 15 in the thin film transistor to cause an oxidation reaction with the silicon constituent of the polycrystalline silicon layer. This causes a silicon oxide film 22 to be formed on the surface of polycrystalline silicon layer 15. If silicon oxide film 22 is formed, the thickness of polycrystalline silicon layer 15 is reduced, and, in the worst case, the polycrystalline silicon is partially lost. In addition, such oxidation of polycrystalline silicon layer 15 is not generated uniformly in the surface of a wafer, so that it causes the polycrystalline silicon layer to have different thicknesses for respective thin film transistors. If the thickness of polycrystalline silicon layer 15 is reduced, the resistance is increased particularly in source/drain regions 15b, 15b and the interconnection part continuous with them. Furthermore, the uneven thickness of polycrystalline silicon layer 15 in the surface of the wafer causes a problem of diversification in characteristics of respective transistors. On the other hand, if the conditions of the heat treatment for flattening are mitigated in order to solve the problem as described above which is caused by the heat treatment for flattening second interlayer insulating layer 16, the flatness of the surface of second interlayer insulating layer 16 is impaired. This causes large steps to be formed on the surface of the interconnection layer formed on second interlayer insulating layer 16. As a result, patterning of the interconnecting layer becomes difficult, accuracy of the interconnection pattern declines, and, in an extreme case, a problem of disconnection arises.